Information Security
MISTY Mystery Tour
Research & Development
Symmetric-key Encryption
 
 
Hardware performance
The results of an evaluation of MISTY’s hardware implementation are as follows:


Implementation Evaluation Environment
Development language: Verilog-HDL
Simulator: Verilog-XL
ASIC (Design library): Mitsubishi Electric 0.18_m CMOS ASIC library
(Logic synthesis and function evaluation): Design compiler version 2000.11-SP1
FPGA (Target FPGA): Xilinx Virtex1000E Series
(Logic synthesis): Synplify version 6.2.4
(Function evaluation): Alliance version3.3.08i

 
(1) ASIC Evaluation Result (No pipeline implementation)
Throughput priority
Throughput: 2,800.9 [Mbps]
Area size: 71.11 [Kgate]
Throu./area: 39.39 [Kbps/gate]
Latency: 1 [Cycles]
Area priority
Throughput: 78.4 [Mbps]
Area size: 6.10 [Kgate]
Throu./area: 12.85 [Kbps/gate]
Latency: 35
Throughput/area priority
Throughput: 1,642.7 [Mbps]
Area size: 16.94 [Kgate]
Throu./area: 97.00 [Kbps/gate]
Latency: 8

(2) FPGA Evaluation Result (Pipeline implementation)
Throughput priority
Throughput: 13,330.6 [Mbps]
Area size: 6,432 [Slice]
Throu./area: 2,072.5
[Kbps/slice]Latency: 82 [Cycles]
Area Priority
Throughput: 250.9 [Mbps]
Area size: 1,462 [Slice]
Throu./area: 171.6 [Kbps/slice]
Latency: 8 [Cycles]
Throughput/area priority (Pipeline implementation)
Throughput: 13,330.6 [Mbps]
Area size: 6,432 [Slice]
Throu./area: 2,072.5 [Kbps/slice]
Latency: 82 [Cycles]



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Software performance
MISTY 1’s (8 layers) encrypting speed is as follows:

Platform: Pentium III (800 MHz)
Language: Assembler
Key schedule: 230 cycles/key
Encryption: 207 cycles/block
Key schedule (Bit slice implementation): 46 cycles/key
Encryption (Bit slice implementation): 169 cycles/block

Platform: Alpha 21264 (667 MHz)
Language: Assembler
Key schedule: 200 cycles/key
Encryption: 197 cycles/block
Key schedule (Bit slice implementation): 17 cycles/key
Encryption (Bit slice implementation): 71 cycles/block

Platform: M16C (20 MHz)
Language: Assembler
Key schedule: 743 cycles/key
Encryption: 1,877 cycles/block
ROM size: 3,400 bytes
RAM size: 64 bytes

Platform: H8/300 (3.57 MHz)
Language: Assembler
Key schedule: 1,240 cycles/key
Encryption: 6,018 cycles/block
ROM size: 1,934 bytes
RAM size: 43 bytes

Platform: Z80 (5 MHz)
Language: Assembler
Language: Assembler
Key schedule: 3,283 cycles/key
Encryption: 13,553 cycles/block
ROM size: 1,992 bytes (Includes 1,152 bytes SBOX)
RAM size: 72 bytes




 
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